1. Field of the Invention
This invention relates to a semiconductor device having a P-channel metal oxide silicon (PMOS) transistor and an N-channel metal oxide silicon (NMOS) transistor and to a liquid crystal display using the semiconductor device as a peripheral drive circuit and the MOS (PMOS or NMOS) transistor as a pixel electrode switching device.
2. Description of the Related Art
With the recent rapid progress of semiconductor technology, there has been a demand for smaller, high-speed and small-power-consumption semiconductor devices and apparatuses using such devices. The development of complementary MOS (CMOS) inverters using P-channel and N-channel enhancement type MOS field effect transistors (FET) as load and inverter devices among such apparatuses is being further promoted because the power consumption of this type of inverter is very small, although a complicated manufacturing process is required.
FIG. 1(a) shows an example of a CMOS inverter in section. A transistor 16 is an NMOS transistor while a transistor 17 is a PMOS transistor. The transistors 16 and 17 are formed on a substrate while being insulated by a base insulation layer 2 and separated from each other by SiO.sub.2 3. The MOS transistor 16 is constituted of an N.sup.+ drain 5, a P-channel region 10, an N-type field limiting regions 12, 12', a gate insulation film 8, a gate electrode 9, a source electrode 14, and a drain electrode 15. The gate electrode is ordinarily formed of a polycrystalline Si, and the source and drain electrodes are formed of Al.
The PMOS transistor 17 is constituted of a P.sup.+ drain 6, a P.sup.+ source 7, N-channel region 11, a P-type field limiting regions 13, 13', a gate insulation film 8', a gate electrode 9', a source electrode 14', and a drain electrode 15'.
FIG. 1(b) is an equivalent circuit diagram of the above-described CMOS inverter. As illustrated, the drain electrode 15 of the NMOS transistor 16 and the drain electrode 15' of the PMOS transistor 17 are connected to a common output electrode. An output voltage at this output electrode is represented by V.sub.out. The source electrode 14 of the NMOS transistor 16 is connected to a low-voltage power supply, while the source electrode 14' of the PMOS transistor 17 is connected to a high-voltage power supply. The voltages of these power supplies are represented by V.sub.SS and V.sub.DD. The substrate 1 forms gate electrodes of parasitic MOS transistors with respect to the NMOS transistor 16 and the PMOS transistor 17. That is, a parasitic PMOS transistor having a gate insulation layer corresponding to the base insulation layer 2, a channel region corresponding to the region 11, and a source and a drain corresponding to the drain 6 and the source 7 is formed, while a parasitic NMOS transistor having a gate insulation layer corresponding to the base insulation layer 2, a channel region corresponding to the region 10, and a source and a drain corresponding to the source 4 and the drain 5 is formed. V.sub.back in FIG. 1(b) represents a voltage input to these parasitic CMOS transistors.
FIG. 9 shows input-output characteristics of a conventional CMOS inverter. In the case of conventional CMOS inverters, it is difficult to increase the absolute value of threshold voltages of parasitic MOS transistors. If the threshold values of the parasitic NMOS and PMOS transistors are V.sub.thbn, and V.sub.thbp, respectively, V.sub.thbn -V.sub.thbp (the threshold value of the PMOS transistor being ordinarily negative)&gt;V.sub.DD -V.sub.SS, that is, V.sub.SS &lt;V.sub.SS +V.sub.thbn &lt;V.sub.DD +V.sub.thbp &lt;V.sub.DD. With respect to any value of V.sub.back, the parasitic NMOS or PMOS transistor can operate. As shown in FIG. 9, in the case where V.sub.in becomes closer to V.sub.DD when V.sub.back is about zero, the parasitic PMOS transistor is operating and a leak current through the PMOS transistor inhibits the output from completely dropping to V.sub.SS. On the other hand, in the case where V.sub.in becomes closer to V.sub.SS when V.sub.back is about 3 V, the parasitic NMOS transistor is operating and a leak current through the NMOS transistor inhibits the output from completely rising to V.sub.DD.
As described above, a leak current flows by the operation of a parasitic CMOS transistor in the conventional CMOS inverter, resulting in failure to obtain an ideal input-output characteristic of the transistor.
For manufacture of a semiconductor device, monocrystal Si having a high carrier mobility is desirable in terms of high-speed driving performance. Conventionally, a SIMOX (separation by implanted oxygen) method has been used to form a monocrystal Si layer on an insulation layer. The thickness of the base insulation layer attained by this method is at most 500 nm. To increase the absolute value of the threshold value, it is necessary to increase the thickness of the base insulation layer according to a relationship between the base insulation layer thickness and the threshold value described later. However, it has been impossible to increase the base insulation layer thickness to a value greater than 500 nm for this manufacturing problem.